Typically, the process of producing semiconductor silicon wafers includes subjecting wafers which are obtained by cutting out and slicing a pulled silicon single crystal ingot to beveling, mechanical polishing (lapping), etching, mirror polishing (polishing) and rinsing steps, and the wafers having highly accurate flatness are produced.
Silicon wafers that have being subjected to mechanical processing steps such as block cutting, outer diameter grinding, slicing and lapping have a damaged layer that is a processing damaged layer in their surfaces. In device production processes, the processing damaged layer induces slip dislocation and other crystal defects, and also the processing damaged layer decreases wafer mechanical strength, and has a detrimental effect on electrical characteristics. Therefore they must be removed.
Etching treatment is performed to remove this processing damaged layer. Examples of the etching treatment includes a batch-type acid etching in which the damaged layer is chemically removed by immersing a plurality of wafers in an etching tank containing a mixed acid or other etching liquid, and a batch-type alkaline etching in which the damaged layer is chemically removed by immersing wafers in an etching tank containing a NaOH or other alkaline etching liquid.
More specifically, as shown in FIG. 10, in the batch-type acid etching, at first a plurality of wafers 1a are held vertically in a holder 1, and this holder 1 is lowered as shown with the solid line arrow in FIG. 10. Then, the wafers are immersed in an aqueous acid etching solution 2a such as a mixed acid contained in an etching tank 2, thereby removing the damaged layers in the wafer surfaces with the aqueous etching solution. Subsequently, the holder 1 which holds the wafers 1a that are immersed in the aqueous etching solution 2a for a predetermined amount of time is pulled up as shown with the broken line arrow in FIG. 10. Next, the holder 1 which holds the wafers 1a that have been subjected to the acid etching is lowered as shown with the solid line arrow in FIG. 10, and the wafers 1a are immersed in a rinsing liquid 3a such as a pure water contained in a rinsing tank 3 so as to remove the aqueous etching solution adhered to the surfaces of the wafers. Subsequently, the holder 1 which holds the wafers 1a that are immersed in the rinsing solution 3a for a predetermined amount of time is pulled up as shown with the broken line arrow in FIG. 10, and then the silicon wafers 1a are dried.
The batch-type acid etching enables the damaged layer to be etched while improving the wafer surface roughness; however, the flatness obtained by lapping ends up being impaired, and there is the problem of the formation of waviness in the order of several millimeters and surface irregularities which are referred to as peelings in the etched surface. In addition, the batch-type alkaline etching enables etching of the damaged layer while maintaining the wafer flatness; however, pits having a local depth of several micrometers and measuring several to several tens of micrometers in size (hereinafter referred to as “facets”) are formed, which cause the problem of worsening wafer surface roughness.
As shown in FIG. 9, as an example of a process for solving these problems, a wafer processing process and wafers processed by this process have been proposed which includes subjecting semiconductor wafers that are obtained by slicing a single crystal ingot to at least beveling 5, lapping 6, etching 7, 8, mirrored surface polishing 9 and rinsing, wherein the etching includes alkaline etching 7 and acid etching 8 after the alkaline etching 7, and the etching amount of the alkaline etching 7 is made to be greater than that of the acid etching 8 (see, for example, Patent Document 1).
In accordance with the process indicated in Patent Document 1, the flatness after lapping can be maintained, and surface waviness after the etching can be reduced, thereby the formation of locally deep pits and the worsening of surface roughness can be inhibited. Moreover, chemically etched wafers can be produced which have etched surfaces that are resistant to the occurrence of contamination by particles, stains and the like. Such wafers enable the polishing allowance for mirror polishing to be reduced, and also their flatness can be improved.
In processes of the prior arts including the process indicated in Patent Document 1, wafers that have being etched is subjected to a double-sided simultaneous polishing step or a single-sided polishing step so as to process their surfaces to a mirrored surfaces. However, the wafer flatness at the time when the planarization step is completed can not be maintained in the front surface and the rear surface of the silicon wafers on which the etching has been completed. Also, the desired wafer surface roughness can not be obtained. Therefore, a large polishing allowance is required in the double-sided simultaneous polishing step and the single-sided polishing step so as to improve wafer flatness and wafer surface roughness. Thereby, a considerable load has been placed on the double-sided simultaneous polishing step and the single-side polishing step.
Patent Document 1 Japanese Patent Application, First Publication No. H11-233485 (claim 1 and paragraph [0042])